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ISL25700
6
FN6885.0
September 3, 2010
V
DAC_OFFSET
 
Offset
DAC register set to 0, No load
0
0.2
1
LSB
 
(Note 7)
R
OUT
DAC Output Impedance
350
?/DIV>
PSRR
Power Supply Rejection Ratio   DAC at middle scale, frequency
from 0Hz to 25kHz
-85
dB
TC
V
 
(Notes 10,
11)
Temperature Coefficient
DAC register set between 20 hex
and FF hex
?5
ppm/癈
Analog Specifications    Over recommended operating conditions unless otherwise stated. Boldface limits apply over 
the operating temperature range, -40癈 to +125癈.  (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 6)
MAX
(Note 13)   UNITS
Operating Specifications  Over the recommended operating conditions unless otherwise specified. Boldface limits 
apply over the operating temperature range, -40癈 to +125癈.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 6)
MAX
(Note 13)  UNITS
I
DD1
V
DD
 Supply Current
(Non-Volatile Write/read)
f
SCL
 = 400kHz; SDA = Open;
(for I
2
C, Active, Read and Write
States) I
PMOS
= 0mA, DAC unload
4
mA
I
DD2
V
DD
 Supply Current
(Volatile Write/read)
I
PMOS
= 0mA, DAC unload
2.8
mA
I
LkgDig
Leakage Current, at SDA and
SCL Pins
Voltage at pin from GND to VCC
-2
2
糀
t
DAC
 
(Note 11)
DAC Settling Time
From bus STOP condition to V
DAC
 
change
3
約
V
POR
Power-On Recall Voltage
Minimum V
DD
 at which memory recall
occurs
2.5
2.9
V
V
DD
Ramp  V
DD
 Ramp Rate
@ any level from 0V to 15V
0.2
50
V/ms
t
D
 
(Note 11)
Power-Up Delay
V
DD
 above V
POR
, to DAC Register recall
completed, and I
2
C Interface in
standby state
1
ms
EEPROM SPECIFICATIONS
EEPROM Endurance
10,000
Cycles
EEPROM Retention
Temperature d +55癈
50
Years
Temperature d +125癈
10
Years
SERIAL INTERFACE SPECIFICATIONS
V
I2C
I
2
C Bus Voltage
V
I2C
 d V
DD
2.7
5.5
V
V
IL
SDA, and SCL Input Buffer
LOW Voltage
V
I2C
from 2.7V to 5.5V
0.8
V
V
IH
SDA, and SCL Input Buffer
HIGH Voltage
V
I2C
from 2.7V to 5.5V
1.4
V
Hysteresis
 
(Note 11)
SDA and SCL Input Buffer
Hysteresis
0.05*V
I2C
V
V
OL
 
(Note 11)
SDA Output Buffer LOW
Voltage, Sinking 4mA
0
0.4
V
Cpin
 
(Note 11)
SDA, and SCL Pin Capacitance
10
pF
f
SCL
SCL Frequency
400
kHz
t
IN
 
(Note 11)
Pulse Width Suppression Time
at SDA and SCL Inputs
Any pulse narrower than the max spec
is suppressed
50
ns
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